1. Field of the Invention
The present invention relates in general to a semiconductor device, and more particularly, to a word line structure with a single-sided partially recessed gate structure.
2. Description of the Related Art
A dynamic random access memory (DRAM) is a common semiconductor memory device widely employed in electronic products. In order to increase the density of the memory devices and improve performance thereof, the size of memory devices must be reduced. The fabrication of conductive plugs connected to the bit lines and disposed between the word lines, however, becomes more difficult as memory device geometries continue to decrease in size. Therefore, many self-aligned processes have been developed for bit line contact fabrication, which are useful for the fabrication of the subsequent conductive plug. If the gate capping layer and the gate spacer of the word line are over etched during fabrication of the self-aligned bit line contact, a short circuit between the word line and the subsequent conductive plug may occur. Conversely, if the gate capping layer and the gate spacer of the word line are under etched during fabrication of the self-aligned bit line contact, the bit line contact may fail, resulting in an open circuit of the bit line after formation of the conductive plug with poor electrical connection.
In order to solve such problems, a word line structure with a double-sided partially recessed gate structure has been suggested. FIGS. 1a to 1e are cross-sections showing a conventional method of forming a word line structure with a double-sided partially recessed gate structure for a DRAM.
First, in FIG. 1a, a silicon substrate 100 is provided. The substrate 100 may contain semiconductor devices, such as capacitors and resistors, used in the memory devices. Here, in order to simplify the diagram, only a flat substrate is depicted. A pair of adjacent gate structures 110 is formed on the silicon substrate 100 for the fabrication of the word lines. The gate structure 110 can be a stacked layer comprising a gate dielectric layer 102, a first gate layer 104, a second gate layer 106, and a gate capping layer 108. The gate dielectric layer 102 can be a silicon oxide layer. The first gate layer 104 can be a polysilicon layer. The second gate layer 106 can be a tungsten silicide layer which serves as a portion of the gate electrode to reduce contact resistance thereof. The gate capping layer 108 can be a silicon nitride layer.
Next, in FIG. 1b, opposing sidewalls of the second gate layer 106 are etched by suitable chemical solution to form a double-sided partially recessed second gate layer 106a with a width less than the overlying gate capping layer 108 and the underlying first gate layer 104, constituting a double-sided partially recessed gate structure 110a. During etching, however, the gate dielectric layer 102 of the gate structure 110a is also etched, resulting in undercut, as depicted by the arrows 111 in FIG. 1b, and decreasing device properties.
Next, in FIG. 1c, an insulating layer 112, such as a silicon nitride layer, is conformably formed on the substrate 200 and the surfaces of both gate structures 110a by conventional deposition, such as chemical vapor deposition (CVD).
Next, in FIG. 1d, an anisotropic etching, such as reactive ion etching (RIE), is performed on the insulating layer 112 to form a gate spacer 112a over opposing sidewalls of each gate structure 110a and expose the surface of the substrate 100, then the fabrication of the word lines is completed.
Thereafter, a dielectric layer (not shown), such as a borophosphosilicate glass (BPSG) layer, is formed overlying the substrate 100 covering each gate structure 110a and each gate spacer 112a. Next, the dielectric layer is etched using the gate capping layers 108 as etching stop layers to leave a portion of dielectric layer 114. Another dielectric layer 116, such as a tetraethyl orthosilicate (TEOS) oxide layer, is deposited on the gate structures 110a and the remaining dielectric layer 114. Next, a photoresist pattern layer 118 is formed on the dielectric layer 116 by conventional photolithography, leaving an opening 120 to expose a bit line contact region.
Finally, in FIG. 1e, the dielectric layers 116 and 114 under the opening 120 are successively removed to form a bit line contact 122 exposing the surface of the substrate 100. Next, a copper layer (not shown) is deposited on the dielectric layer 116 and fills the bit line 122. The copper layer is subsequently removed by chemical mechanical polishing (CMP) using the dielectric layer 116 as an etching stop layer, to leave a portion of copper layer 124 serving as a conductive plug to electrically connect the bit line (not shown) with the substrate 100.
However, in this method, since the second gate layer 106 is partially etched prior to the formation of the bit line contact 122, the top area of the double-sided partially recessed second gate layer 106a is significantly reduced, increasing the contact resistance of the word line.